![]() Abstract: The invention discloses a NAND flash controller, including a command and address data transmission channel adapted to connect the bus timing interface with the channel selector and transmit command and address data, a data buffer region adapted to receive message data from the bus timing interface through system bus, a control register adapted to receive an operation parameter configured through system bus via the bus timing interface, a logic controller adapted to write the data information into or read the data information from the data buffer region according to the operation parameter, a channel selector adapted to connect the DMA data transmission channel or the command and address data transmission channel according to the operation parameter for transmitting data.
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